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| Quad Voltage Up and Down Sequencer and Monitor with Programmable Timing ADM1186 FEATURES Powered from 2.7 V to 5.5 V on the VCC pin Monitors four supplies via 0.8% accurate comparators Digital core supports up and down supply sequencing Multiple devices can be cascaded (ADM1186-1) Four inputs can be programmed to monitor different voltage levels with resistor dividers Capacitor programmable supply sequence time delays and a timeout delay to 5% accuracy at 25C Four open-drain enable outputs Open-drain power-good output Open-drain sequence complete pin and bidirectional open-drain fault pin (ADM1186-1 only) GENERAL DESCRIPTION The ADM1186-1 and ADM1186-2 are integrated, four-channel voltage monitoring and sequencing devices. A 2.7 V to 5.5 V power supply is required on the VCC pin for power. Four precision comparators, VIN1 to VIN4, monitor four voltage rails. All four comparators share a 0.6 V reference and have a worst-case accuracy of 0.8%. Resistor networks that are external to the VIN1, VIN2, VIN3, and VIN4 pins set the undervoltage (UV) trip points for the monitored supply rails. The ADM1186-1 and ADM1186-2 have four open-drain enable outputs, OUT1 to OUT4, that are used to enable power supplies. An open-drain power-good output, PWRGD, indicates whether the four VINx inputs are above their UV thresholds. A state machine monitors the state of the UP and DOWN pins on the ADM1186-1 or the UP/DOWN pin on the ADM1186-2 to control the supply sequencing direction (see Figure 2). In the WAIT START state, a rising edge transition on the UP or UP/DOWN pin triggers a power-up sequence. A falling edge transition on the DOWN or UP/DOWN pin in the POWER-UP DONE state triggers a power-down sequence. APPLICATIONS Monitor and alarm functions Up and down power supply sequencing Telecommunication and data communication equipment PCs, servers, and notebook PCs APPLICATION DIAGRAM 5V EN 5V EN 3.3V AUX 3.3V AUX 1F 5V 100nF 3.3V AUX VCC FAULT SEQUENCE CONTROL UP DOWN OUT1 OUT2 OUT3 OUT4 VIN1 VIN2 VIN3 VIN4 2.5V AUX PWRGD GND SEQ_DONE 3.3V AUX EN 5V ADP1706 IN OUT 2.5V 5V ADP2107 IN OUT 1.8V 3.3V AUX EN ADP1821 IN OUT 1.2V 5V ADP1706 IN OUT 3.3V ADM1186-1 DLY_EN_OUT1 DLY_EN_OUT2 DLY_EN_OUT3 DLY_EN_OUT4 BLANK_DLY Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved. 07153-003 ADM1186 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Application Diagram........................................................................ 1 Revision History ............................................................................... 2 Specifications..................................................................................... 4 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 13 UVLO Behavior.......................................................................... 13 Power-Up Sequencing and Monitoring................................... 13 Operation in POWER-UP DONE State.................................. 14 Power-Down Sequencing and Monitoring ............................. 14 Input Glitch Filtering ................................................................. 14 Fault Conditions and Fault Handling ...................................... 14 Defining Time Delays................................................................ 15 Sequence Control Using a Supply Rail .................................... 16 Cascading Multiple Devices.......................................................... 23 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 26 REVISION HISTORY 5/08--Revision 0: Initial Version Rev. 0 | Page 2 of 28 ADM1186 During a power-up sequence, the state machine enables each power supply in turn. The supply output voltage is monitored to determine whether it rises above the UV threshold level within a user defined duration called the blanking time. If a supply rises above the UV threshold, the next enable output in the sequence is turned on. In addition to the blanking time, the user can also define a sequence time delay before each enable output is turned on. The ADM1186-1 provides an open-drain pin, SEQ_DONE, that is asserted high to provide an indication that a power-up sequence is complete. The SEQ_DONE pin allows multiple cascaded ADM1186-1 devices to perform controlled power-up and power-down sequences. During a power-down sequence, the enable outputs turn off in reverse order. The same sequence time delays used during the power-up sequence are also used during the power-down sequence as each enable output is turned off; no blanking time is used during a power-down sequence. At the end of a powerdown sequence, the SEQ_DONE pin is brought low. During sequencing and when powered up, the state machine continuously monitors the part for any fault conditions. Faults include a UV condition on any of the inputs or an unexpected control input. Any fault causes the state machine to enter a fault handler, which immediately turns off all enable outputs and then ensures that the device is ready to start a new power-up sequence. The ADM1186-1 has a bidirectional pin, FAULT, that facilitates fault handling when using multiple devices. If an ADM1186-1 experiences a fault condition, the FAULT pin is driven low, causing other connected ADM1186-1 devices to enter their own fault handling states. The ADM1186-1 is available in a 20-lead QSOP package, and the ADM1186-2 is available in a 16-lead QSOP package. POWER-DOWN DONE WAIT START SEQUENCE UP TRIGGER SEQUENCE SUPPLY 1 ON SEQUENCE SUPPLY 1 OFF FAULT HANDLER SEQUENCE SUPPLY 2 ON SEQUENCE SUPPLY 2 OFF FAULT CONDITION OCCURS IN ANY STATE SEQUENCE SUPPLY 3 ON SEQUENCE SUPPLY 3 OFF SEQUENCE SUPPLY 4 ON SEQUENCE SUPPLY 4 OFF SEQUENCE DOWN TRIGGER POWER-UP DONE Figure 2. Simplified State Machine Diagram Rev. 0 | Page 3 of 28 07153-004 ADM1186 SPECIFICATIONS VVCC = 2.7 V to 5.5 V, TA = -40C to +85C; typical values at TA = 25C, unless otherwise noted. Table 1. Parameter VCC PIN Operating Voltage Range, VVCC Undervoltage Lockout, VUVLO Undervoltage Lockout Hysteresis Supply Current, IVCC VIN1 TO VIN4 (VINx) PINS Input Current Input Threshold 1 Input Glitch Immunity Positive Glitch Duration Negative Glitch Duration UP, DOWN, AND UP/DOWN PINS Input Current Input Threshold Input Glitch Immunity DLY_EN_OUTx AND BLANK_DLY PINS Time Delay Accuracy Time Delay Charge Current Time Delay Threshold Time Delay Discharge Resistor OUT1 TO OUT4 (OUTx) PINS Output Low Voltage, VOUTL Leakage Current VVCC That Guarantees Valid Outputs 1 Min 2.7 Typ 3.3 2.46 50 146 Max 5.5 Unit V V mV A nA nA V s s nA V s s % A V Test Conditions/Comments VVCC falling Steady state; sequence complete VVINx = 0 V to 1 V VVINx = 0 V to 5.5 V; VVINx can be greater than VVCC 210 +25 +100 0.6048 33.2 6.6 +100 -25 -100 0.5952 19.9 2.75 -100 1.372 3.3 2.7 0.6000 26.6 4.7 50 mV input overdrive 50 mV input overdrive VUP/DOWN = 0 V to 5.5 V; VUP/DOWN can be greater than VVCC 100 mV input overdrive 1 V input overdrive External capacitor values of 10 nF to 2.2 F; excludes external capacitor tolerance 1.4 6.8 4.9 5 14 1.4 450 1.428 9.7 7.9 9 0.4 1 1 V A V VVCC = 2.7 V, ISINK = 2 mA OUTx = 5.5 V Output is guaranteed to be either low (VOUTL = 0.4 V) or giving a valid output level from VVCC = 1 V, ISINK = 30 A or VVCC = 1.1 V, ISINK = 100 A VVCC = 2.7 V, ISINK = 2 mA PWRGD = 5.5 V Output is guaranteed to be either low (VPWRGDL = 0.4 V) or giving a valid output level from VVCC = 1 V, ISINK = 30 A or VVCC = 1.1 V, ISINK = 100 A PWRGD PIN Output Low Voltage, VPWRGDL Leakage Current VVCC That Guarantees Valid Outputs 0.4 1 1 V A V FAULT PIN Input Threshold1 Input Glitch Immunity Output Low Voltage, VFAULTL Leakage Current VVCC That Guarantees Valid Outputs 1.372 3.1 1.4 5.6 1.428 8.1 0.4 1 V s V A V 1 V input overdrive VVCC = 2.7 V, ISINK = 2 mA FAULT = 5.5 V Output is guaranteed to be either low (VFAULTL = 0.4 V) or giving a valid output level from VVCC = 1 V, ISINK = 30 A or VVCC = 1.1 V, ISINK = 100 A 1 Rev. 0 | Page 4 of 28 ADM1186 Parameter SEQ_DONE PIN Output Low Voltage, VSEQ_DONEL Leakage Current VVCC That Guarantees Valid Outputs Min Typ Max 0.4 1 1 Unit V A V Test Conditions/Comments VVCC = 2.7 V, ISINK = 2 mA SEQ_DONE = 5.5 V Output is guaranteed to be either low (VSEQ_DONEL = 0.4 V) or giving a valid output level from VVCC = 1 V, ISINK = 30 A or VVCC = 1.1 V, ISINK = 100 A Includes input glitch filter and all other internal delays 50 mV input overdrive 50 mV input overdrive 50 mV input overdrive 100 mV input overdrive 1 V input overdrive 1 V input overdrive UP, UP/DOWN held low RESPONSE TIMING VINx to PWRGD VINx Going Low to High VINx Going High to Low VINx to FAULT, OUTx Low VINx Going High to Low (UV Fault) UP, DOWN, and UP/DOWN to FAULT, OUTx Low, tUDOUT External FAULT to OUTx Low Fault Hold Time 1 21.9 5.8 6.1 5.5 5.8 35 28.8 7.3 7.5 8.6 7.7 44 35.2 8.9 9.2 12.1 10.5 10 54 s s s s s s s Input comparators do not include hysteresis on their inputs. The comparator output passes through a digital glitch filter to remove short transients from the input signal that would otherwise drive the state machine. Rev. 0 | Page 5 of 28 ADM1186 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 2. Parameter VCC Pin VINx Pins UP, DOWN, UP/DOWN Pins DLY_EN_OUTx, BLANK_DLY Pins PWRGD, SEQ_DONE, OUTx Pins FAULT Pin Operating Temperature Range Storage Temperature Range Lead Temperature Convection Reflow Peak Temperature Time at Peak Temperature Junction Temperature Rating -0.3 V to +6 V -0.3 V to +6 V -0.3 V to +6 V -0.3 V to VCC + 0.3 V -0.3 V to +6 V -0.3 V to +6 V -40C to +85C -65C to +150C 260C 30 sec 125C Table 3. Thermal Resistance Package Type 16-Lead QSOP 20-Lead QSOP JA 149.97 125.80 Unit C/W C/W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 6 of 28 ADM1186 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS GND VIN1 VIN2 VIN3 VIN4 UP DOWN FAULT DLY_EN_OUT1 1 2 3 4 5 6 7 8 9 20 19 18 VCC OUT1 OUT2 OUT3 OUT4 PWRGD SEQ_DONE BLANK_DLY 07153-005 GND 1 16 15 VCC OUT1 OUT2 OUT3 OUT4 PWRGD BLANK_DLY DLY_EN_OUT4 07153-006 VIN1 2 VIN2 3 VIN3 4 VIN4 5 UP/DOWN 6 DLY_EN_OUT2 DLY_EN_OUT3 7 8 ADM1186-1 TOP VIEW (Not to Scale) 17 16 15 14 13 12 11 ADM1186-2 TOP VIEW (Not to Scale) 14 13 12 11 10 9 DLY_EN_OUT4 DLY_EN_OUT3 DLY_EN_OUT2 10 Figure 3. ADM1186-1 Pin Configuration Figure 4. ADM1186-2 Pin Configuration Table 4. Pin Function Descriptions Pin No. ADM1186-1 ADM1186-2 1 1 2 2 Mnemonic GND VIN1 Description Chip Ground Pin. Noninverting Comparator Input. The voltage on this pin is compared with a 0.6 V reference. Can be used to monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine. Noninverting Comparator Input. The voltage on this pin is compared with a 0.6 V reference. Can be used to monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine. Noninverting Comparator Input. The voltage on this pin is compared with a 0.6 V reference. Can be used to monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine. Noninverting Comparator Input. The voltage on this pin is compared with a 0.6 V reference. Can be used to monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine. Noninverting Comparator Input. A rising edge on this pin initiates a power-up sequence when the ADM1186-1 is in the WAIT START state. Noninverting Comparator Input. A falling edge on this pin initiates a power-down sequence when the ADM1186-1 is in the POWER-UP DONE state. Noninverting Comparator Input. A rising edge on this pin initiates a power-up sequence when the ADM1186-2 is in the WAIT START state. A falling edge on this pin initiates a power-down sequence when the ADM1186-2 is in the POWER-UP DONE state. Active Low, Bidirectional, Open-Drain Pin. When an internal fault is detected by the ADM1186-1 state machine, this pin is asserted low and the SET FAULT state is entered. An external device pulling this pin low also causes the ADM1186-1 to enter the SET FAULT state. Timing Input. The capacitor connected to this input sets the time delay between the UP input initiating a power-up sequence and OUT1 being asserted high. During a powerdown sequence, this input sets the time delay between OUT1 being asserted low and SEQ_DONE being asserted low. Timing Input. The capacitor connected to this input sets the time delay between VIN1 coming into compliance and OUT2 being asserted high during a power-up sequence. During a power-down sequence, this input sets the time delay between OUT2 being asserted low and OUT1 being asserted low. Timing Input. The capacitor connected to this input sets the time delay between VIN2 coming into compliance and OUT3 being asserted high during a power-up sequence. During a power-down sequence, this input sets the time delay between OUT3 being asserted low and OUT2 being asserted low. 3 3 VIN2 4 4 VIN3 5 5 VIN4 6 7 6 UP DOWN UP/DOWN 8 FAULT 9 DLY_EN_OUT1 10 7 DLY_EN_OUT2 11 8 DLY_EN_OUT3 Rev. 0 | Page 7 of 28 ADM1186 Pin No. ADM1186-1 ADM1186-2 12 9 Mnemonic DLY_EN_OUT4 Description Timing Input. The capacitor connected to this input sets the time delay between VIN3 coming into compliance and OUT4 being asserted high during a power-up sequence. During a power-down sequence, this input sets the time delay between OUT4 being asserted low and OUT3 being asserted low. Timing Input. The capacitor connected to this input sets the blanking time. This is the time allowed between OUTx being asserted and VINx coming into compliance; otherwise, the SET FAULT state is entered. Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. When the power-up sequence is complete, SEQ_DONE is asserted high. During a power-down sequence, the pin remains asserted until the time delay set by DLY_EN_OUT1 has elapsed. When a fault occurs, this pin is asserted low. Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. The output state of this pin is a logical AND function of the UV threshold state of the VINx pins. When the voltage on all VINx inputs exceeds 0.6 V, PWRGD is asserted. This output is driven low if the voltage on any VINx pin is below 0.6 V. Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. During a power-up sequence, this output is asserted high after the time delay set by the capacitor on DLY_EN_OUT4 has elapsed. The output is asserted low immediately after a powerdown sequence has been initiated. Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. During a power-up sequence, this output is asserted high after the time delay set by the capacitor on DLY_EN_OUT3 has elapsed. During a power-down sequence, the output is asserted low after the time delay set by the capacitor on DLY_EN_OUT4 has elapsed. Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. During a power-up sequence, this output is asserted high after the time delay set by the capacitor on DLY_EN_OUT2 has elapsed. During a power-down sequence, the output is asserted low after the time delay set by the capacitor on DLY_EN_OUT3 has elapsed. Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. During a power-up sequence, this output is asserted high after the time delay set by the capacitor on DLY_EN_OUT1 has elapsed (ADM1186-1) or immediately after a rising edge on UP/DOWN (ADM1186-2). During a power-down sequence, the output is asserted low after the time delay set by the capacitor on DLY_EN_OUT2 has elapsed. Positive Supply Input Pin. The operating supply voltage range is 2.7 V to 5.5 V. 13 10 BLANK_DLY 14 SEQ_DONE 15 11 PWRGD 16 12 OUT4 17 13 OUT3 18 14 OUT2 19 15 OUT1 20 16 VCC Rev. 0 | Page 8 of 28 ADM1186 TYPICAL PERFORMANCE CHARACTERISTICS 160 140 POSITIVE GLITCH DURATION (s) 120 100 80 60 40 20 07153-007 38 36 34 32 30 VCC = 3.3V 28 26 24 22 SUPPLY CURRENT (A) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 5.5 0 50 100 OVERDRIVE (mV) 150 200 Figure 5. Supply Current vs. Supply Voltage 150 VCC = 5.5V Figure 8. VINx Input Positive Glitch Immunity vs. Input Overdrive 18 16 NEGATIVE GLITCH DURATION (s) 145 SUPPLY CURRENT (A) 14 12 10 8 6 VCC = 3.3V 4 2 140 VCC = 3.3V 135 VCC = 2.7V 130 125 07153-008 -20 0 20 40 TEMPERATURE (C) 60 80 0 50 100 OVERDRIVE (mV) 150 200 Figure 6. Supply Current vs. Temperature 605 604 Figure 9. VINx Input Negative Glitch Immunity vs. Input Overdrive 31.0 30.5 POSITIVE GLITCH DURATION (s) VINX INPUT THRESHOLD (mV) 603 602 601 600 599 598 597 596 07153-009 30.0 29.5 29.0 28.5 28.0 27.5 27.0 26.5 VCC = 3.3V VCC = 3.3V -20 0 20 40 TEMPERATURE (C) 60 80 -20 0 20 40 TEMPERATURE (C) 60 80 Figure 7. VINx Input Threshold vs. Temperature Figure 10. VINx Input Positive Glitch Immunity vs. Temperature Rev. 0 | Page 9 of 28 07153-012 595 -40 26.0 -40 07153-011 120 -40 0 07153-010 0 20 ADM1186 6.0 5.8 10.0 9.5 INPUT GLITCH DURATION (s) NEGATIVE GLITCH DURATION (s) 5.6 5.4 5.2 5.0 4.8 4.6 4.4 4.2 07153-013 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 VCC = 3.3V VCC = 3.3V -20 0 20 40 TEMPERATURE (C) 60 80 -20 0 20 40 TEMPERATURE (C) 60 80 Figure 11. VINx Input Negative Glitch Immunity vs. Temperature Figure 14. UP, DOWN, and UP/DOWN Input Glitch Immunity vs. Temperature 10.0 9.5 1.43 1.42 INPUT GLITCH DURATION (s) 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 VCC = 3.3V THRESHOLD (V) 1.41 VCC = 3.3V 1.40 1.39 1.38 07153-014 -20 0 20 40 TEMPERATURE (C) 60 80 0 200 400 600 OVERDRIVE (mV) 800 1000 Figure 12. UP, DOWN, UP/DOWN, FAULT, and Time Delay Trip Threshold vs. Temperature 10.0 9.5 INPUT GLITCH DURATION (s) INPUT GLITCH DURATION (s) Figure 15. FAULT Input Glitch Immunity vs. Input Overdrive 7.0 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 07153-015 6.5 6.0 VCC = 3.3V 5.5 VCC = 3.3V 0 50 100 OVERDRIVE (mV) 150 200 -20 0 20 40 TEMPERATURE (C) 60 80 Figure 13. UP, DOWN, and UP/DOWN Input Glitch Immunity vs. Input Overdrive Figure 16. FAULT Input Glitch Immunity vs. Temperature Rev. 0 | Page 10 of 28 07153-018 5.0 5.0 -40 07153-017 1.37 -40 5.0 07153-016 4.0 -40 5.0 -40 ADM1186 15.0 14.8 400 350 OUTPUT LOW VOLTAGE (mV) VCC = 5.5V 14.6 CHARGE CURRENT (A) 14.4 14.2 14.0 13.8 13.6 13.4 13.2 VCC = 3.3V 300 250 200 150 100 50 1mA VCC = 2.7V 07153-019 -20 0 20 TEMPERATURE (C) 40 60 2.0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 5.5 Figure 17. Time Delay Charge Current vs. Temperature 1k Figure 20. Output Low Voltage vs. Supply Voltage 9.0 8.5 8.0 TIME DELAY (ms) 100 RESPONSE TIME (s) 7.5 7.0 6.5 6.0 5.5 10 07153-020 100 CAPACITOR (nF) 1k 10k 3.2 3.7 4.2 4.7 SUPPLY VOLTAGE (V) 5.2 Figure 18. Time Delay vs. Capacitor Value 600 Figure 21. VINx to FAULT, OUTx Low Response Time vs. Supply Voltage 9.0 8.5 500 OUTPUT LOW VOLTAGE (mV) 400 RESPONSE TIME (s) VCC = 2.7V 8.0 7.5 7.0 6.5 6.0 5.5 07153-021 300 VCC = 3.3V 200 VCC = 5.5V 100 0 5 10 15 OUTPUT SINK CURRENT (mA) 20 25 -20 0 20 40 TEMPERATURE (C) 60 80 Figure 19. Output Low Voltage vs. Output Sink Current Figure 22. VINx to FAULT, OUTx Low Response Time vs. Temperature Rev. 0 | Page 11 of 28 07153-024 0 5.0 -40 07153-023 1 10 5.0 2.7 07153-022 13.0 -40 100A 0 1.0 1.5 ADM1186 30 10.0 9.5 25 RESPONSE TIME (s) RESPONSE TIME (s) VCC = 3.3V 9.0 8.5 8.0 7.5 7.0 6.5 07153-025 20 15 10 0 50 100 OVERDRIVE (mV) 150 200 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 Figure 23. VINx to FAULT, OUTx Low Response Time vs. Input Overdrive Figure 24. UP, DOWN, UP/DOWN to FAULT, OUTx Low Response Time vs. Supply Voltage Rev. 0 | Page 12 of 28 07153-026 5 6.0 2.5 ADM1186 THEORY OF OPERATION The operation of the ADM1186 is described in the following sections. Where necessary, differences between the ADM1186-1 and the ADM1186-2 are noted. Figure 28 is a detailed functional block diagram of the ADM1186-1, and Figure 30 is a detailed functional block diagram of the ADM1186-2. The operation of the ADM1186 is described in the context of a typical voltage monitoring and sequencing application, as shown in Figure 1. This example uses the ADM1186-1, because it is essentially a superset of the functionality of the ADM1186-2. In the example application, the ADM1186-1 turns on four regulators, monitors four separate voltage rails, and generates a power-good signal to turn on a microcontroller when all power supplies are on and above their UV threshold level. Figure 34 shows a typical ADM1186-2 voltage sequencing and monitoring application. After the fault hold time elapses, the state machine moves to the CLEAR FAULT state. If the UP (ADM1186-1) or UP/DOWN (ADM1186-2) pin is low, the state machine can exit the CLEAR FAULT state. This change is indicated on the ADM1186-1 by the FAULT pin being asserted high. For the ADM1186-2, there is no external indication that the part is ready to perform sequencing, so 0.5 ms should be allowed after VCC comes up before attempting to start a power-up sequence. POWER-UP SEQUENCING AND MONITORING In the example shown in Figure 1, the main supply of 3.3 V powers up the device via the VCC pin. The state machine remains in the WAIT START state until either a rising edge on the UP pin initiates a power-up sequence, or a fault condition occurs. The ADM1186-2 requires a rising edge on the UP/DOWN pin to start a power-up sequence. If a rising edge on the UP pin is detected, the state machine moves to the DELAY 1 state. The ADM1186-2 does not have a DLY_EN_OUT1 pin, so it omits the DELAY 1 state. Figure 29 shows the ADM1186-1 state machine in detail; Figure 31 shows the ADM1186-2 state machine. The waveforms for a typical power-up and power-down sequence when no faults occur are shown in Figure 32 (ADM1186-1) and Figure 33 (ADM1186-2). In the DELAY 1 state, a time delay, set by the capacitor connected to the DLY_EN_OUT1 pin, is allowed to elapse. Then, in the ENABLE OUT1 state, the OUT1 pin is asserted high. OUT1 is an open-drain, active high output, and in this application it enables the output of a 2.5 V regulator. During the ENABLE OUT1 state, the VIN1 pin monitors the 2.5 V supply after a blanking delay, set by the capacitor on the BLANK_DLY pin. The blanking delay, which is the same for all supplies, is set to allow the slowest rising supply sufficient time to switch on. UVLO BEHAVIOR The ADM1186 is designed to ensure that the outputs are always in a known state for a VCC supply voltage of 1 V or greater; if the VCC supply voltage is below 1 V, the state of the outputs is not guaranteed. Figure 25 shows the behavior of the outputs over the full VCC supply range. VCC 5.5V UNDER STATE MACHINE CONTROL 2.7V VUVLO ALL OUTPUTS LOW UVLO ACTIVE 1V 07153-027 OUTPUTS NOT GUARANTEED 0V Figure 25. ADM1186 Output Behavior over VCC Supply As the VCC supply begins to rise, an undervoltage lockout (UVLO) circuit becomes active and begins to pull the outputs of the ADM1186 low. The outputs are not guaranteed to be low until the VCC supply has reached 1 V. State machine operation is also disabled, so it is not possible to initiate a power-up sequence. This behavior ensures that enable pins on dc-to-dc converters or point-of-load (POL) devices connected to the OUTx pins are held low as the supplies are rising. This prevents the dc-to-dc converters or the POLs from switching on briefly and then switching off as the supply rails stabilize. When VCC rises above VUVLO and the internal reference is stable, the UVLO circuit enables the state machine. The state machine takes control of the outputs and begins operation from the SET FAULT state. An external resistor divider scales the supply voltage down for monitoring at the VIN1 pin (see Figure 26). The resistor ratio is selected so that the VIN1 voltage is 0.6 V when the supply voltage rises to the UV level at start-up (a voltage below the nominal 2.5 V level). In Figure 26, R1 is 7.4 k and R2 is 2.5 k, so a voltage level of 2.375 V corresponds to 0.6 V on the noninverting input of the first comparator. V 2.5V 2.375V 0V 2.375V SUPPLY GIVES 0.6V AT VIN1 PIN t R1 7.4k VIN1 ADM1186 07153-028 R2 2.5k 0.6V TO LOGIC CORE Figure 26. Setting the Undervoltage Threshold with an External Resistor Divider Rev. 0 | Page 13 of 28 ADM1186 If the output of the 2.5 V regulator meets the UV level when the blanking time elapses, the state machine continues the power-up sequence, moving into the DELAY 2 state. A time delay, set by the capacitor connected to the DLY_EN_OUT2 pin, elapses before turning on the next enable output, OUT2, in the ENABLE OUT2 state. If the 1.8 V supply does not rise to the UV level before the blanking time elapses, sequencing immediately stops and the state machine enters the SET FAULT state. The same scheme is implemented with the other output and input pins. Every supply turned on via an output pin, OUTx, is monitored via an input pin, VINx, to check that the supply has risen above the UV level within the blanking time before the state machine moves on to the next supply. When a supply is on and operating correctly, the ADM1186 continues to monitor it for the duration of the power-up sequence. If any supply drops below its UV threshold level during a power-up sequence, sequencing stops and the state machine enters the SET FAULT state. When the state machine is in the WAIT START state, or at any time during a power-up sequence, a falling edge on the DOWN pin (ADM1186-1) or the UP/DOWN pin (ADM1186-2) generates a fault. The PWRGD pin is asserted high, independently of the state machine, when all four VINx pins are above their UV threshold. The state machine in the ADM1186-1 indicates that the powerup sequence is complete by asserting the SEQ_DONE pin high. This sequence of steps is repeated until all four regulators are switched off and the device is in the WAIT START state. Because the ADM1186-2 does not have a DLY_EN_OUT1 pin, there is no delay between the OUT1 pin being brought low and the state machine returning to the WAIT START state. When the device is in the WAIT START state, the SEQ_DONE pin is brought low. During a power-down sequence, the state machine monitors the supplies that are still on. If a supply drops below its UV threshold before it is turned off, the power-down sequence immediately stops and the state machine enters the SET FAULT state. A rising edge on the UP or UP/DOWN pin during a powerdown sequence generates a fault. The PWRGD pin is asserted low, independently of the state machine power-down sequence, when one or more of the VINx pins drops below 0.6 V. INPUT GLITCH FILTERING The VINx, UP, DOWN, and FAULT inputs on the ADM1186-1 and the VINx and UP/DOWN inputs on the ADM1186-2 use a time-based glitch filter to prevent false triggering. The glitch filter avoids the need to use some of the operating supply range to provide hysteresis on an input. This helps to maximize the available operating supply range for a system, which is especially important in systems where low supply voltages are being used. The VINx inputs use a positive glitch filter that is approximately five times longer than the negative glitch filter. This provides additional glitch immunity during the power-up sequence as a supply is rising, but still allows for a quick response in the event of an undervoltage event on an input. OPERATION IN POWER-UP DONE STATE When the power-up sequence is complete, the state machine remains in the POWER-UP DONE state until one of the following events occurs: * A falling edge occurs on the DOWN (ADM1186-1) or UP/DOWN (ADM1186-2) pin, initiating a power-down sequence. An undervoltage condition occurs on one or more of VIN1 to VIN4, generating a fault. A rising edge occurs on the UP pin, generating a fault (ADM1186-1 only). An external device brings the FAULT pin low, causing a fault (ADM1186-1 only). FAULT CONDITIONS AND FAULT HANDLING During supply sequencing and operation in the POWER-UP DONE state, the ADM1186 continuously monitors the VINx, UP, DOWN, and UP/DOWN pins for fault conditions. The FAULT pin on the ADM1186-1 is monitored to detect external faults generated by other devices, which is important during cascade operation. The following faults are internally generated: * A supply fails to reach the UV threshold within the time defined by the BLANK_DLY capacitor during a power-up sequence. A UV condition occurs on VINx after the blanking time has elapsed during a power-up sequence. A UV condition occurs on VINx before the supply is disabled during a power-down sequence. A falling edge occurs on the DOWN or UP/DOWN pin during a power-up sequence or in the WAIT START state. A rising edge occurs on the UP or UP/DOWN pin during a power-down sequence or in the POWER-UP DONE state. * * * POWER-DOWN SEQUENCING AND MONITORING When the ADM1186 is in the POWER-UP DONE state, a falling edge on the DOWN or UP/DOWN pin initiates a power-down sequence (see Figure 29 or Figure 31). The state machine moves to the DISABLE OUT4 state, bringing the OUT4 pin low and switching off the 3.3 V regulator. A time delay, set by the capacitor on the DLY_EN_OUT4 pin, elapses before the state machine moves to the DISABLE OUT3 state. * * * * Rev. 0 | Page 14 of 28 ADM1186 The action taken by the ADM1186 state machine is the same for an internal or external fault. The state machine enters the SET FAULT state, asserts the SEQ_DONE and FAULT pins low (ADM1186-1 only), and asserts all four OUTx enable pins low. The ADM1186 remains in the SET FAULT state for the fault hold time before moving into the CLEAR FAULT state. If the UP or UP/DOWN pin is low for a time of t tUDOUT before the state machine enters the CLEAR FAULT state, the state machine can move immediately into the WAIT ALL OK state. The length of time from entering the SET FAULT state to reaching the WAIT ALL OK state, with the UP or UP/DOWN pin held low, is the fault hold time. The fault hold time is the minimum amount of time that the FAULT pin is held low. If the UP or UP/DOWN pin is high when the state machine enters the CLEAR FAULT state, the time that the FAULT pin is held low is extended. When the ADM1186-1 is in the CLEAR FAULT state and the UP pin is low, the WAIT ALL OK state is entered and the FAULT pin is deasserted. If an external device is driving the FAULT pin low, the state machine remains in the WAIT ALL OK state until the FAULT pin returns high. The state machine then transitions into the WAIT START state, ready for the next power-up sequence. The blanking time is controlled by the capacitor on the BLANK_DLY pin. This capacitor sets the time allowed between an enable output being asserted, turning on a supply, and the output of the supply rising above its defined UV threshold. A constant current source is connected to a capacitor through a switch that is under the control of the state machine. This current source charges a capacitor until the threshold voltage is reached. For all capacitors, the duration of the time delay is defined by the following formula: tDELAY = CDELAY x 0.1 where: tDELAY is the time delay in seconds. CDELAY is the capacitor value in microfarads (F). For capacitor values from 10 nF to 2.2 F, the time delay is in the range of 1 ms to 220 ms. If a capacitor is not connected to a timing pin, the time delay is minimal, in the order of several microseconds. When a capacitor is not being charged by the current source, it is connected via a resistor to ground. Each capacitor has a dedicated resistor with a typical value of 450 . To ensure accurate time delays, time must be allowed for a capacitor to discharge after it has been used. Typically, allowing five RC time constants is sufficient for the capacitor to discharge to less than 1% of the threshold voltage. If the capacitors are not sufficiently discharged after use, the time delays will be smaller than expected. This can happen if very small capacitor values are used or if a power-up or powerdown sequence is performed immediately after another sequence has been completed. Examples of when this behavior can occur include, but are not limited to, the following: * * A power-down sequence is initiated immediately after entering the POWER-UP DONE state. A fault occurs in the ENABLE OUT1 state when the DLY_EN_OUT1 capacitor is charged and a power-up sequence is started very quickly after the fault has been handled. The DLY_EN_OUTx time delay is very short and is insufficient to allow the BLANK_DLY capacitor to fully discharge. DEFINING TIME DELAYS The ADM1186 allows the user to define sequence and blanking time delays using capacitors. The ADM1186-1 has four DLY_EN_OUTx pins, and the ADM1186-2 has three DLY_EN_OUTx pins. Capacitors connected to these pins control the time delay between supplies turning on or off during the power-up and power-down sequences. Both devices provide one pin (BLANK_DLY) to set the blanking time delay. The ADM1186-1 has a pin called DLY_EN_OUT1 that the ADM1186-2 does not have. The capacitor on this pin sets the time delay used before enabling OUT1 during a power-up sequence, as well as the time delay between disabling OUT1 and returning to the WAIT START state during a power-down sequence. Although this time delay is not essential when a single ADM1186-1 device is used, the time delay is essential when multiple devices are cascaded (see the Cascading Multiple Devices section). When ADM1186-1 devices are used in cascade, the capacitor on the DLY_EN_OUT1 pin of Device N + 1 sets the sequence time delay between the last supply of Device N and the first supply of Device N + 1 being turned on and off. During the power-up sequence, the capacitors connected to the DLY_EN_OUTx pins set the time from the end of the blanking period to the next enable output being asserted high. During the power-down sequence, the capacitors set the time between consecutive enable outputs being asserted low. * To achieve the best timing accuracy over the operational temperature range, the choice of capacitor is critical. Capacitors are typically specified with a value tolerance of 5%, 10%, or 20%, but in addition to the value tolerance, there is also a variation in capacitance over temperature. Where high accuracy timing is important, the use of capacitors that use a C0G, sometimes called NPO, dielectric results in a capacitance variation of only 0.3% over the full temperature range. This capacitance variation contrasts with typical variations of 15% for X5R and X7R dielectrics and 22% for X7S capacitor dielectrics. Rev. 0 | Page 15 of 28 ADM1186 SEQUENCE CONTROL USING A SUPPLY RAIL The UP and DOWN inputs on the ADM1186-1 and the UP/DOWN input on the ADM1186-2 are used to initiate power-up and power-down sequences. These inputs are designed for use with digital or analog signals, such as power supply rails. Using a power supply rail to control the up and down sequencing allows the ADM1186 to perform sequencing and monitoring functions for five supply rails. When using a supply rail to control an ADM1186-1 (with the UP and DOWN pins connected) or an ADM1186-2, some hysteresis is required. The hysteresis is added on the joined UP and DOWN pins of the ADM1186-1 or on the UP/DOWN pin of the ADM1186-2 to ensure that a slowly ramping supply rail does not cause spurious rising or falling edges that would otherwise cause state machine faults. To provide the necessary hysteresis, a single additional resistor (RH in Figure 27) is connected between the joined UP and DOWN pins of the ADM1186-1 and the OUT1 pin of the device, or between the UP/DOWN pin of the ADM1186-2 and the OUT1 pin of the device. RH VIN 3.3V VP R2 VSHYS = (VH - VL ) x R1 + R2 In the example application shown in Figure 27, the following values could be used: RP = 10 k VP = 5 V VIN = 3.3 V The values of the R1 and R2 resistors determine the midpoint of the hysteresis, VMID, about which VH and VL set the levels at which power-up and power-down sequences are initiated. For a 3.3 V supply, a threshold just below 3 V could be used, making R1 = 11 k and R2 = 10 k and giving a midpoint of 2.94 V. V MID = VIN x R2 3.3 x 10 k = R1 + R2 11 k+ 10 k VMID = 2.94 V As a general rule, the value for RH is approximately 60 times the value of R1 in parallel with R2. In this example, R1 in parallel with R2 is 5.24 k, so RH would be approximately 314 k. Taking a value of 300 k for RH and using this value in the previous equations for VH, VL, and VSHYS, the following values are obtained: R1 ADM1186-1 + UP VCC OUT1 RP 10 k + 300 k VH = 1.4 x 1 + 11 k x 10 k x 300 k VH = 2.991 V R2 DOWN 07153-038 Figure 27. Using a Supply Rail to Control Sequencing with Hysteresis When OUT1 is low, the resistor RH sinks current from the node at the midpoint of R1 and R2, slightly increasing the VIN voltage needed to start a power-up sequence, referred to as VH. When OUT1 is high, RH sources current into the midpoint of R1 and R2, decreasing the VIN voltage necessary to start a power-down sequence, referred to as VL. The hysteresis at the VIN node is simply VH - VL. As the R1 and R2 resistors scale VIN down, the hysteresis on VIN is also scaled down. The scaled hysteresis, VSHYS, at the inputs to the UP and DOWN pins (ADM1186-1) or the UP/DOWN pin (ADM1186-2) must be at least 75 mV. The value of RH is selected to ensure that this is the case. R2 + RH VH = 1.4 x 1 + R1 x R2 x RH 1.4 VP - 1.4 VL = 1.4 + R1 x - R2 RH + RP - 1.4V - + STATE MACHINE 1.4 5 - 1. 4 VL = 1.4 + 11 k x - 10 k 300 k + 10 k VL = 2.812 V 10 k VSHYS = (2.991 - 2.812 ) x 11 k + 10 k VSHYS = 0.085 V Because the value of VSHYS is greater than the 75 mV of scaled hysteresis required, the RH resistor value selected is sufficient. If the value of VSHYS obtained is too small, the value of RH can be reduced, increasing the scaled hysteresis provided. It should be noted that it is not possible to directly connect the VCC supply to the UP pin (ADM1186-1) or to the UP/DOWN pin (ADM1186-2) to start a sequence as the VCC comes up. When the UVLO circuit enables the state machine, it begins in the fault handler states. To reach the WAIT START state so that sequencing can begin, the UP pin (ADM1186-1) or the UP/DOWN pin (ADM1186-2) must be held low after the state machine is enabled. Rev. 0 | Page 16 of 28 ADM1186 VCC VIN1 GLITCH FILTER ADM1186-1 PWRGD VIN2 GLITCH FILTER VIN3 GLITCH FILTER OUT1 GLITCH FILTER VIN4 0.6V UP GLITCH FILTER RISING EDGE DETECT STATE MACHINE GLITCH FILTER FALLING EDGE DETECT OUT2 OUT3 DOWN OUT4 FAULT GLITCH FILTER 1.4V SEQ_DONE 14A DLY_EN_OUT1 DLY_EN_OUT2 DLY_EN_OUT3 DLY_EN_OUT4 BLANK_DLY 450 CAPACITOR MUX AND DISCHARGE 1.4V 07153-029 GND Figure 28. Functional Block Diagram of the ADM1186-1 Rev. 0 | Page 17 of 28 ADM1186 FAULT IN: HIGH WAIT ALL OK FAULT OUT: HIGH UP: LOW WAIT START FAULT IN: LOW OUT1: LOW OUT4: LOW OUT2: LOW SEQ_DONE: LOW DOWN: FALLING EDGE OUT3: LOW FAULT OUT: HIGH UP: RISING EDGE FAULT IN: LOW DOWN: FALLING EDGE CLEAR FAULT F FAULT HOLD TIMES OUT SET FAULT DELAY 1 F OUT1: LOW OUT4: LOW OUT2: LOW SEQ_DONE: LOW OUT3: LOW FAULT OUT: LOW AFTER DLY_EN_OUT1 TIME DELAY AFTER DLY_EN_OUT1 TIME DELAY FAULT IN: LOW DOWN: FALLING EDGE AFTER BLANKING DELAY VIN1: LOW F F EXIT UVLO F FAULT IN: LOW UP: RISING EDGE DISABLE OUT1 OUT1: LOW ENABLE OUT1 OUT1: HIGH AFTER BLANKING DELAY VIN1: HIGH FAULT IN: LOW DOWN: FALLING EDGE VIN1: LOW DELAY 2 F AFTER DLY_EN_OUT2 TIME DELAY FAULT IN: LOW UP: RISING EDGE VIN1: LOW AFTER DLY_EN_OUT2 TIME DELAY FAULT IN: LOW DOWN: FALLING EDGE VIN1: LOW AFTER BLANKING DELAY VIN2: LOW F DISABLE OUT2 OUT2: LOW ENABLE OUT2 OUT2: HIGH F AFTER BLANKING DELAY VIN2: HIGH DELAY 3 FAULT IN: LOW DOWN: FALLING EDGE VIN1 OR VIN2: LOW F AFTER DLY_EN_OUT3 TIME DELAY FAULT IN: LOW UP: RISING EDGE VIN1 OR VIN2: LOW F AFTER DLY_EN_OUT3 TIME DELAY FAULT IN: LOW DOWN: FALLING EDGE VIN1 OR VIN2: LOW AFTER BLANKING DELAY VIN3: LOW DISABLE OUT3 OUT3: LOW ENABLE OUT3 OUT3: HIGH F AFTER BLANKING DELAY VIN3: HIGH FAULT IN: LOW DOWN: FALLING EDGE VIN1 OR VIN2 OR VIN3: LOW DELAY 4 F AFTER DLY_EN_OUT4 TIME DELAY FAULT IN: LOW UP: RISING EDGE VIN1 OR VIN2 OR VIN3: LOW AFTER DLY_EN_OUT4 TIME DELAY FAULT IN: LOW DOWN: FALLING EDGE VIN1 OR VIN2 OR VIN3: LOW AFTER BLANKING DELAY VIN4: LOW F DISABLE OUT4 OUT4: LOW ENABLE OUT4 OUT4: HIGH F AFTER BLANKING DELAY VIN4: HIGH FAULT IN: LOW UP: RISING EDGE VIN1 OR VIN2 OR VIN3 OR VIN4: LOW POWER-UP DONE DOWN: FALLING EDGE SEQ_DONE: HIGH F Figure 29. ADM1186-1 State Machine Operation Rev. 0 | Page 18 of 28 07153-030 ADM1186 VCC VIN1 GLITCH FILTER ADM1186-2 PWRGD VIN2 GLITCH FILTER VIN3 GLITCH FILTER OUT1 VIN4 GLITCH FILTER OUT2 0.6V UP/DOWN GLITCH FILTER EDGE DETECT STATE MACHINE OUT3 1.4V OUT4 14A DLY_EN_OUT2 DLY_EN_OUT3 DLY_EN_OUT4 BLANK_DLY 450 CAPACITOR MUX AND DISCHARGE 1.4V 07153-031 GND Figure 30. Functional Block Diagram of the ADM1186-2 Rev. 0 | Page 19 of 28 ADM1186 WAIT START OUT1: LOW OUT3: LOW OUT2: LOW OUT4: LOW UP/DOWN: RISING EDGE UP/DOWN: FALLING EDGE UP/DOWN: LOW CLEAR FAULT F FAULT HOLD TIMES OUT F UP/DOWN: RISING EDGE DISABLE OUT1 OUT1: LOW ENABLE OUT1 AFTER BLANKING DELAY VIN1: LOW OUT1: HIGH AFTER BLANKING DELAY VIN1: HIGH UP/DOWN: FALLING EDGE VIN1: LOW SET FAULT DELAY 2 AFTER DLY_EN_OUT2 TIME DELAY F OUT1: LOW OUT3: LOW OUT2: LOW OUT4: LOW AFTER DLY_EN_OUT2 TIME DELAY UP/DOWN: RISING EDGE VIN1: LOW UP/DOWN: FALLING EDGE VIN1: LOW AFTER BLANKING DELAY VIN2: LOW F F EXIT UVLO F DISABLE OUT2 OUT2: LOW ENABLE OUT2 OUT2: HIGH AFTER BLANKING DELAY VIN2: HIGH UP/DOWN: FALLING EDGE VIN1 OR VIN2: LOW DELAY 3 AFTER DLY_EN_OUT3 TIME DELAY F AFTER DLY_EN_OUT3 TIME DELAY UP/DOWN: RISING EDGE VIN1 OR VIN2: LOW UP/DOWN: FALLING EDGE VIN1 OR VIN2: LOW AFTER BLANKING DELAY VIN3: LOW F DISABLE OUT3 OUT3: LOW ENABLE OUT3 OUT3: HIGH F AFTER BLANKING DELAY VIN3: HIGH UP/DOWN: FALLING EDGE VIN1 OR VIN2 OR VIN3: LOW DELAY 4 AFTER DLY_EN_OUT4 TIME DELAY F AFTER DLY_EN_OUT4 TIME DELAY UP/DOWN: RISING EDGE VIN1 OR VIN2 OR VIN3: LOW UP/DOWN: FALLING EDGE VIN1 OR VIN2 OR VIN3: LOW AFTER BLANKING DELAY VIN4: LOW F DISABLE OUT4 OUT4: LOW ENABLE OUT4 OUT4: HIGH F AFTER BLANKING DELAY VIN4: HIGH UP/DOWN: FALLING EDGE POWER-UP DONE VIN1 OR VIN2 OR VIN3 OR VIN4: LOW F Figure 31. ADM1186-2 State Machine Operation Rev. 0 | Page 20 of 28 07153-032 ADM1186 1 UP DOWN DLY_EN_OUT1 OUT1 DLY_EN_OUT2 OUT2 DLY_EN_OUT3 OUT3 DLY_EN_OUT4 OUT4 BLANK_DLY SEQ_DONE PWRGD 2 3 4 5 6 7 8 9 10 11 12 13 14 1 STATE NAMES 1 - WAIT START 2 - DELAY 1 3 - ENABLE OUT1 4 - DELAY 2 5 - ENABLE OUT2 6 - DELAY 3 7 - ENABLE OUT3 8 - DELAY 4 9 - ENABLE OUT4 10 - POWER-UP DONE 11 - DISABLE OUT4 12 - DISABLE OUT3 07153-033 13 - DISABLE OUT2 14 - DISABLE OUT1 Figure 32. ADM1186-1 Typical Power-Up and Power-Down Sequence Waveforms with Corresponding State Names 1 2 3 4 5 6 7 8 9 10 11 12 13 1 UP/DOWN OUT1 DLY_EN_OUT2 OUT2 DLY_EN_OUT3 OUT3 DLY_EN_OUT4 OUT4 BLANK_DLY PWRGD 1 - WAIT START 2 - ENABLE OUT1 3 - DELAY 2 4 - ENABLE OUT2 5 - DELAY 3 6 - ENABLE OUT3 STATE NAMES 7 - DELAY 4 8 - ENABLE OUT4 9 - POWER-UP DONE 10 - DISABLE OUT4 11 - DISABLE OUT3 12 - DISABLE OUT2 Figure 33. ADM1186-2 Typical Power-Up and Power-Down Sequence Waveforms with Corresponding State Names Rev. 0 | Page 21 of 28 07153-037 13 - DISABLE OUT1 ADM1186 5V EN 5V EN 3.3V AUX 3.3V AUX 1F 5V 100nF VCC SEQUENCE CONTROL OUT1 OUT2 OUT3 OUT4 VIN1 VIN2 VIN3 VIN4 EN 5V ADP1706 IN OUT 2.5V 5V ADP2107 IN OUT 1.8V 3.3V AUX EN ADP1821 IN OUT 1.2V 5V ADP1706 IN OUT 3.3V UP/DOWN ADM1186-2 DLY_EN_OUT2 DLY_EN_OUT3 DLY_EN_OUT4 BLANK_DLY GND 2.5V AUX PWRGD 07153-034 Figure 34. ADM1186-2 Typical Application Rev. 0 | Page 22 of 28 ADM1186 CASCADING MULTIPLE DEVICES Multiple ADM1186-1 devices can be cascaded in applications that require more than four supplies to be sequenced and monitored. When ADM1186-1 devices are cascaded, the controlled power-up and power-down of all the cascaded supplies is maintained using only three pins on each device. There are several configurations for interconnecting these devices. The most suitable configuration depends on the application. Figure 35 and Figure 36 show two methods for cascading multiple ADM1186-1 devices. Figure 35 shows a single sequence of 12 supplies. The capacitors used for timing are not shown in the figure for clarity. To ensure controlled power-up and power-down sequencing of all 12 supplies, the following connections are made: * * * The UP pin of the first device and the DOWN pin of the last device in the cascade chain are connected. The SEQ_DONE pin of Device N is connected to the UP pin of Device N + 1. The SEQ_DONE pin of Device N is connected to the DOWN pin of Device N - 1. Figure 36 shows two independent sequences of four supplies, each with common status outputs. In this example, both devices share the same sequence control signal, so they start their power-up and power-down sequences at the same time. Both devices must complete their power-up sequences before the POWER GOOD signal goes high. The FAULT pins of all devices in a cascade should be connected. Connecting the FAULT pins ensures that an undervoltage fault on one device, or an unexpected event such as a rising or falling edge on the UP or DOWN pin, generates a fault condition on all the other devices. When an internal fault condition occurs on a device, it pulls its FAULT pin low. This in turns causes the other ADM1186-1 devices to enter the SET FAULT state and pull their FAULT pins low. Each device waits for the fault hold time to elapse and then moves to the CLEAR FAULT state. If the VCC supply for an ADM1186-1 drops below VUVLO, the UVLO circuit becomes active, and the FAULT pin is pulled low. This generates a fault condition on all other connected devices. A device in the CLEAR FAULT state holds its FAULT pin low until its UP input pin is low. The device then moves into the WAIT ALL OK state and releases the FAULT pin. If, for example, a UV fault occurs on a VINx pin during a power-up sequence, the UP pin will be high on the first device in the cascade. The first device in the cascade holds the FAULT line low until the UP pin is brought low. All other devices will have released their FAULT pins and will be in the WAIT ALL OK state. When the UP pin goes low, the first device releases its FAULT pin so the FAULT line returns high, which allows all devices to move together from the WAIT ALL OK state back into the WAIT START state, ready for the next power-up sequence. An external device such as a microcontroller, field programmable gate array (FPGA), or an overtemperature sensor can cause a fault condition by briefly bringing FAULT low. In this case, the ADM1186-1 behaves as described. If the external device continues to hold the FAULT line low, all the ADM1186-1 devices remain in the WAIT ALL OK state, effectively preventing a power-up sequence from starting. When the SEQUENCE CONTROL line goes high, Device A begins the power-up sequence, turning on each enable output in turn, with the associated delays, according to the state machine. When Device A completes its power-up sequence, the SEQ_DONE pin goes from low to high, initiating a power-up sequence on Device B. When Device B completes its power-up sequence, the Device B SEQ_DONE pin goes high, initiating a power-up sequence on Device C. When Device C completes its power-up sequence and all supplies are above the UV threshold, the system POWER GOOD signal goes high. If the SEQUENCE CONTROL line goes low, Device C starts a power-down sequence, turning off its enable outputs. When all Device C enable outputs are off, the SEQ_DONE pin on Device C goes low, causing a high-to-low transition on the DOWN pin of Device B. This transition initiates a power-down sequence on Device B, which takes all its OUTx pins low, causing SEQ_DONE to be taken low. This high-to-low transition is seen by Device A, which starts its power-down sequence, thus completing the ordered shutdown of the 12 supplies. Note that the capacitor on the DLY_EN_OUT1 pin of Device B (not shown in Figure 35) sets the sequence time delay between the last supply of Device A and the first supply of Device B being turned on and off. Rev. 0 | Page 23 of 28 ADM1186 3.3V 3.3V VCC VCC VCC ADM1186-1A OUT1 V5 OUT1 OUT2 V11 VIN3 VIN4 OUT3 OUT4 UP FAULT DOWN PWRGD OUT3 VIN1 VIN2 OUT2 OUT1 V6 V9 V10 ADM1186-1B EN1 EN2 V7 ADM1186-1C EN5 EN6 EN7 3.3V V12 EN9 EN10 EN11 EN12 V1 VIN1 VIN2 VIN3 VIN4 OUT4 UP DOWN PWRGD SEQ_DONE GND FAULT VIN1 OUT2 OUT3 3.3V OUT4 FAULT EN4 EN8 V8 V2 VIN2 SUPPLIES SCALED DOWN WITH RESISTOR DIVIDERS V3 EN3 VIN3 V4 VIN4 ENABLE OUTPUTS TO REGULATORS WITH PULL-UPs AS REQUIRED 07153-035 Figure 35. Cascading Multiple ADM1186-1 Devices, Option 1 Rev. 0 | Page 24 of 28 SEQ_DONE GND 3.3V SEQUENCE CONTROL UP DOWN PWRGD POWER GOOD SEQ_DONE GND ADM1186 3.3V VCC ADM1186-1A SUPPLIES SCALED DOWN WITH RESISTOR DIVIDERS V1 V2 V3 V4 VIN1 VIN2 VIN3 VIN4 OUT3 OUT4 UP FAULT EN3 EN4 OUT1 OUT2 EN1 EN2 ENABLE OUTPUTS TO REGULATORS WITH PULL-UPs AS REQUIRED 3.3V SEQUENCE CONTROL DOWN PWRGD SEQ_DONE GND NO CONNECT 3.3V VCC ADM1186-1B V5 V6 V7 V8 VIN1 VIN2 VIN3 VIN4 OUT3 OUT4 UP FAULT POWER GOOD NO CONNECT 07153-036 OUT1 OUT2 EN5 EN6 EN7 EN8 5V DOWN PWRGD SEQ_DONE GND Figure 36. Cascading Multiple ADM1186-1 Devices, Option 2 Rev. 0 | Page 25 of 28 ADM1186 OUTLINE DIMENSIONS 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 20 11 1 10 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.069 (1.75) 0.053 (1.35) SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8 0 0.010 (0.25) 0.006 (0.15) 0.020 (0.51) 0.010 (0.25) 0.025 (0.64) BSC 0.050 (1.27) 0.016 (0.41) 0.041 (1.04) REF COMPLIANT TO JEDEC STANDARDS MO-137-AD CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012808-A Figure 37. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches and (millimeters) 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 16 9 1 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 8 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.069 (1.75) 0.053 (1.35) SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8 0 0.010 (0.25) 0.006 (0.15) 0.020 (0.51) 0.010 (0.25) 0.025 (0.64) BSC 0.050 (1.27) 0.016 (0.41) 0.041 (1.04) REF COMPLIANT TO JEDEC STANDARDS MO-137-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012808-A Figure 38. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model ADM1186-1ARQZ 1 ADM1186-1ARQZ-REEL1 ADM1186-2ARQZ1 ADM1186-2ARQZ-REEL1 EVAL-ADM1186-1EBZ1 EVAL-ADM1186-1MBZ1 EVAL-ADM1186-2EBZ1 EVAL-ADM1186-2MBZ1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 20-Lead Shrink Small Outline Package [QSOP] 20-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] Evaluation Kit Micro-Evaluation Kit Evaluation Kit Micro-Evaluation Kit Package Option RQ-20 RQ-20 RQ-16 RQ-16 Z = RoHS Compliant Part. Rev. 0 | Page 26 of 28 ADM1186 NOTES Rev. 0 | Page 27 of 28 ADM1186 NOTES (c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07153-0-5/08(0) Rev. 0 | Page 28 of 28 |
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